JUNE 2009 Meeting Announcement

 

Date:                    Monday, June 8, 2009

Registration:         5:30 P.M.

Early Bird:           6:00 P.M.    Annual Section Survey Results

Dinner:                 6:30 P.M.

Main Program:     7:30 P.M.    The Use of DOE Techniques for Optimizing the Wire Bonding Process

Cost:                    $20.00 per person

Location:

Chef Alan’s

(Fairgrounds Square Mall)

Reading, PA 19605

610-685-4000

 

This meeting members of the International Microelectronics and Packaging Society (IMAPS) will be our guests.

 

Menu

Buffet which includes:

·        Tossed Garden Salad

·        Salad Dressings & Trimmings

·        Cole Slaw

·        Fresh Fruit Bowl

·        Potato Salad

·        Honey Glazed Roast Chicken

·        Oven Baked lasagna

·        New England Style Haddock

·        Parslied New Red potatoes

·        Vegetable du jour

·        Hot Rolls & Butter

·        Carrot Cake

·        Coffee, Hot Tea, & Ice Tea

·        Adult Beverages - cash bar

 

 

 

Early Bird Presentation:

 

          Frank Yurick, Section Membership Chairman, will review the Section’s Annual Survey results.  Other items of importance to the section will also be discussed.

 

 

Main Program:

 

The Use of DOE Techniques for Optimizing the Wire Bonding Process

 

Abstract

 

          Wire bonding remains the dominant chip interconnect method, with more than 90% of the chip interconnect market place. The ultrasonic weld produced by wire bonding has proven to be a highly reliable and versatile form of interconnection, and the process has continuously evolved to meet the demands of increasingly complex devices.

 

           This presentation will focus on the process variables and the use of Designed Experiments to understand the process.

 

Agenda:

 

·        Wire bonding process variables

·        Testing wire bonds and response variables

·        The use of Designed Experiments to understand a complex process with 4 case studies

·        Experiments for high yield processes

·        Analysis methods

o   DOE Analysis

o   Pareto diagrams

o   Control charts for high yield processes

 

Qualifications

Lee Levine is an internationally recognized semiconductor assembly process expert with over 25 years of targeted experience in technical process development and optimization.  He is known for keen analytical and troubleshooting skills in the creative and effective resolution of problems in production processes.  He consistently produces business results that create enhanced revenue opportunities, higher yields and trouble free operations.

Experience

Previous experience includes 20 years as Principal and Staff Metallurgical Process Engineer at Kulicke & Soffa and Distinguished Member of the Technical Staff at Agere Systems. He was awarded 4 patents, published more than 50 technical papers, and won the 1999 John A. Wagnon Technical Achievement award from the International Microelectronics and Packaging Society, IMAPS.  Major innovations include copper ball bonding, loop shapes for thin, small outline packages (TSOP and TSSOP, and CSPs) and introduction of DOE and statistical techniques for understanding assembly processes.  He is a Fellow, V.P of the Keystone Chapter, and V.P Technology for IMAPS.

Lee is a graduate of Lehigh University, Bethlehem, Pa where he earned a degree in Metallurgy and Materials Engineering.

 

 

Reservations: Call Cori Monighan at 610-582-2222 (Beacon Container) by Friday, June 5, 2009 to make your reservation or e-mail her at c.monighan@beaconcontainer.com.  Please leave your name, meal choice, and company affiliation.

 

          Please remember that we are a non-profit organization.  Have the courtesy to cancel your reservation or you will be billed for the meal.  If you must cancel, call Cori before Noon, on the day of the meeting.  Your cooperation is greatly appreciated.

 

 

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